The present invention is directed to a desynchronizer which alleviates the need for very low bandwidth analog phase lock loops (PLL's) to smooth phase jumps caused by pointer changes on a DS3 signal mapped into a SONET STS-1 payload. A similar desynchronizer can be built using purely analog phase lock loop technology. Another form of a desynchronizer can be designed to extract a DS3 payload from a SONET STS-1 payload which leaks the 8 unit interval (UI) pointer adjustment one bit at a time using fixed leaking digital techniques. The shortcomings of an analog only phase lock loop is that very low analog loop bandwidths are required to reduce the 8 UI phase jump caused by a SONET STS-1 pointer adjustment to levels low enough to meet output payload jitter specifications. Bandwidths in the 1 Hz region are required to reduce jitter content of the output phase transition to levels approximately equal to 1 UI, with lower jitter levels more desirable (but requiring lower bandwidths). Bandwidths this low require extremely large time constants and large filter component values for resistors and capacitors. In addition, they are slow to lock, thereby causing large time delays after transients before the DS3 channel is usable for data transmission again.
Simple fixed bit leakout desynchronizers are adequate to filter waiting time and mapping jitter. There is a digital adjunct circuit which can hide low occurrence "transient" effects, such as pointer adjustments, from the high bandwidth analog phase lock loop. If these transients are not hidden from the high bandwidth phase lock loop, jitter approaching 7 UI pp occurs from a single STS-1 pointer adjustment (an 8 UI step at the STS-1 rate produces a time gap of 8.times.19.3 ns=154 ns, or approximately 7 UI at the DS-3 rate).
While this type of desynchronizer hides the bulk of the pointer movement from the high bandwidth phase lock loop, it equalizes itself by leaking out the original pointer adjustment, one bit at a time into the high bandwidth phase lock loop. This equalization is necessary or the desynchronizer's elastic store would eventually overflow. As each bit is leaked out, usually as fast as possible without exceeding the overall payload jitter specification, jitter from 0.7 to 1.5 UI pp is generated by phase transitions in the output signal. These relatively high levels of jitter have been shown to cause problems in cascaded islands of SONET networks.
The present invention overcomes the above-mentioned difficulties by hiding the pointer adjustments through use of digital filtering techniques to gradually leakout the pointer adjustment. The magnitude of the jitter can be reduced to any arbitrarily low level by adjusting the digital filter's time constant and thus its bandwidth, and by increasing the numerical resolution in the digital filter and supporting digital circuitry.
Thus the present invention has the same net effect as an analog only phase lock loop, except that very low analog phase lock loop bandwidths are not requited. The embodiment of the present invention uses a low bandwidth digital filter, a digital subtractor, a digital to analog function output stage and is coupled to a conventional high bandwidth analog phase lock loop.
The present invention is directed to a desynchronizer for use in a digital communication network wherein an asynchronous rate payload is mapped into a synchronous payload such as that associated with the Synchronous Optical Network (SONET) or the European equivalent thereto, SDH. As defined more fully in American National Standard for Telecommunications, ANSI T1.105-1991, Digital Hierarchy-Optical Interface Rates and Format Specifications and as also explained in Digital Telephony, Second Edition, John Bellamy, Wiley Series in Telecommunications, pointer movements of the synchronous payload envelope associated with a SONET network result from transmission of synchronous data from one network element to another. Such pointer movements in an overall telecommunications network can be modeled as shown in FIG. 1. This model represents a multi-node SONET network in which a DS3 payload is mapped into a SONET synchronous payload envelope at node 0. Nodes 1 to N-1 represent intermediate add/drop multiplexers (ADM's) containing pointer processors. These intermediate nodes each remap the original synchronous payload envelope (SPE) into a SONET frame rate determined by the local node clock (represented by rates f(1) to f(N-1)). Each of these local node clocks has a phase wander known as time interval error (TIE) relative to a stable (or traceable) clock. Thus, random pointer movement occurs on the SPE by the time it arrives at the desynchronizer (node N). A full discussion of network timing performance measurements is presented in Section 7.3.7 of Digital Telephony, Second Edition.
Pointer movements cannot be released immediately at the DS3 output, but rather must be stored in the desynchronizer elastic store and from there gradually leaked out. Pointer arrival statistics are important for elastic store sizing and desynchronizer architecture. Studies have been done in T1X1.6 on pointer statistics assuming TIE levels as set forth in Reference 1 (see Table 1). References 2 and 3 show typical statistical pointer arrivals assuming 2 to 6 byte +/- pointer adjustment thresholds in intermediate pointer processors. These thresholds are in addition to the required minimum of three bytes needed to accommodate the offset between input and output Section plus Line overhead bytes (see ANSI T1.105-1991). Assuming the TIE levels set forth in reference 0, a desynchronizer needs to accommodate four to five pointer arrivals within a one second period which is denoted as the granularity of simulation.
TABLE 1 ______________________________________ REFERENCES ______________________________________ 0. T1X1 LB91-04 Letter Ballot for T1.101 - "Synchro- nization Interface Standard", TIX1.3. 1. T1X1.6/90- New Section 7 for ANSI T1.105a, 009R2, T1X1.3/.6 2. T1X1.6/89-047 "SONET Jitter Measurement Criteria," AT&T 3. T1X1.6/89-057 "Pointer Simulation Parameters," NT1. 4. T1X1.3/90-031 "Proposal for Short-Term Stability Specification of SONET Timing Reference Signals," Bellcore 5. T1X1.3/90-041 "Short Term Stability Specification of Timing Reference Signals at the Input to SONET NE's," PacBell T1X1-LB90-01 "A Technical Report on the Effects of SONET on Payload Output Jitter," T1X1.6 8. T1X1.6/90-005 "STS-1 and OC-N Jitter Proposal," Alcatel 9. T1.105-1991 "Digital Hierarchy - Optical Interface Rates and Formats Specification (SONET), Section 7 Synchronization 10. T1X1.6/88-028 "Analysis of Jitter & Wander Associated with Pointer Adjustments," British Telecom. 11. T1X1.6/88-029 "A Possible Design for a Desynchronizer Accommodating Pointer Adjustments," British Telecom. 12. T1X1.6/89-029 "Results of Simulations of a Possible Desynchronizer Design," British Telecom. 13. T1X1.6/88-026 "A Synchronous Desynchronizer." Bellcore Signals," Bellcore. 14. T1X1.6/88-041 "Pointer Spreading Desynchronizer," Northern Telecom. (14a) T1X1.3/92-071 "Jitter Accumulation Results in SONET Islands for Milli-Hertz NE Clock Bandwidths," Alcatel. (14b) T1X1.3/92-072 "DS3 Payload Output Finer Proposal," Alcatel. (14c) T1X1.3/92-017 "Additional SONET Islands Jitter Simulation Results," Alcatel. (14d) T1X1.3/92-006 "Initial Draft of SONET Jitter Standard," Tellabs. 15. T1 LB280 "A Technical Report on the Effects of SONET on Payload Output Jitter," T1X1.3 16. "Design and Performance Verification of a SONET-TO- DS3 Desynchronizer", Hamlin, Jr., TranSwitch Corp., Shelton, Connecticut, published before February 25, 1992. 17. U.S. Pat. No. 4,996,698 - Nelson - February 26, 1991 18. U.S. Pat. No. 5,052,025 - Duff et al - September 24, ______________________________________ 1991
The present desynchronizer overcomes the above-mentioned difficulties by a desynchronizer architecture based on linear models which can gracefully degrade in performance if normal thresholds are exceeded.